Pranav
Vinoth

Electrical and computer engineering student at CU Boulder. I design RTL, bring it up on FPGAs, and write the testbenches that prove it works.

Looking for a Summer 2027 internship in digital design, verification or FPGA.

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Skills, as a pinout

Pick a pin to see where I've used it.

28 skills across 4 groups.

1st of 26 teams

IEEE Region 5 Student Hardware Competition, circuit design category, Feb 2026. I designed the ESP32 sensor circuit (temperature, humidity, CO2, CO and sound level) and co-built the live multi-device dashboard, judged by industry and IEEE engineers against teams from 20+ universities.

Projects

RV32IM RISC-V CPU with HDMI video controller

Fall 2026

Arty Z7-20

Multi-cycle CPU state machine feeding a frame buffer and HDMI output FetchDecodeExecuteMemoryWriteback Frame bufferHDMI 125 MHz, one clock domain pixel clock enable, divide by 5
  • Designed a multi-cycle RV32IM processor in Verilog around a fetch, decode, execute, memory, writeback state machine.
  • Wrote a self-checking testbench and an 88-case assembly test plan covering the RV32I base ISA and M extension, including divide-by-zero and overflow edge cases.
  • Automated an assembly to hex to simulation regression flow with timeout detection and per-test pass/fail reporting.
  • Built a 640x480 HDMI controller with TMDS encoding and a CPU-writable frame buffer, using a pixel clock enable to avoid clock domain crossing. Demoed Snake running on hardware.
Built with

Ethernet MAC byte-stream parser

Summer 2025

Arty Z7-20, Zynq-7000 SoC

150 µs end to end, PHY to parsed payload

  • Wrote bare-metal C on the Zynq ARM core to pass Ethernet frames over AXI to a SystemVerilog byte-stream parser.
  • Measured end-to-end latency on hardware while extracting payloads from 80-byte frames.
  • Built a UVM environment with an agent (sequencer, driver, monitor) and a scoreboard to verify frame handling.
Built with

Two-layer USB-C phone charger PCB

Spring 2025

Custom board, KiCad

Power path: USB-C input to IP5306 charger to six parallel 18650 cells, then an MT3608 boost stage to 15 V, out through USB-C to a phone USB-C in IP5306 charging and protection MT3608 boost stage L SW C out switching loop kept short 15 V USB-C out Phone reported slow charging 6 x 18650 cells in parallel 3.0 to 4.2 V
  • Designed a two-layer board in KiCad around six 18650 Li-ion cells wired in parallel for capacity, with an IP5306 managing charging and protection from USB-C.
  • Boosted the 3.0 to 4.2 V pack to 15 V with an MT3608, placing the switch, inductor, Schottky diode and capacitors tightly together to keep the high-current switching loop small.
  • Brought up the board after finding that the capacitor footprints didn't match the parts I received, rewiring them with jumper wires instead of waiting on a new board.
  • Tested on a phone, which charged but reported slow charging. Next revision: a USB Power Delivery controller so the phone can negotiate fast charging, and footprints checked against the datasheets of the exact parts ordered.
Built with

Experience

  1. May 2026 to now

    Machine learning researcher, BOLD Lab

    University of Colorado Boulder

    Predicted magnetic core loss at 4.78% error across 4 unseen materials with BelNet and DeepONet models in PyTorch, using excitation waveform, frequency and temperature.

  2. May to Aug 2025

    AWS engineer intern, Exterro

    Coimbatore, India

    Deployed EC2 instances and S3 buckets, managed over SSH on Linux, to store and process document datasets.

  3. May to Aug 2024

    ML engineer intern, Exterro

    Frisco, TX

    Cut document review time by 60% with a TensorFlow classifier that sorts files by type, at 91% accuracy across 50K+ documents.

Education

B.S. Electrical and Computer Engineering, minor in Quantum Engineering

University of Colorado Boulder, expected May 2028

Digital Logic, Programming Digital Systems, Microelectronics, Programming Embedded Systems, Electronics Design Lab, Advanced Circuit Analysis